AES Encryption implemented in an FPGA and optimized for high throughput with a parallel pipelined design.  Target device was pre-production hardware requiring our unique experience working with such systems for early design and development support.

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The increasing availability of open-hardware IP like RISC-V allows the rapid development of custom parallel architectures.  We leverage extensive experience in RISC array processor optimization to develop high-performance embedded computing solutions.

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The deployment of AI solutions in resource constrained systems requires highly optimized solutions.  We develop technology for deploying AI in low-power FPGAs that maximize the compute intensive capability within minimum device-scale resource constraints.

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